This invention relates to interrupt schemes.
Hardware interrupts in Intel-based personal computers, for example, typically force the central processing unit (CPU) to wait while the hardware interrupt controller provides the CPU a complete interrupt vector. Once received, the CPU uses the interrupt vector to address an interrupt handling routine. The waiting period, known as "acknowledge latency," stems from the fact that interrupt controllers generally connect to an input/output (I/O) bus of the microcomputer, and the I/O bus has a much longer access time than the local CPU bus. After the CPU receives notification of an interrupt, and acknowledges this to the interrupt controller, the CPU must wait (without performing other operations) typically 1-2 .mu.sec before it receives the interrupt vector from the interrupt controller. Depending on the speed of the CPU, the acknowledge latency can be as many as 100 CPU clock cycles.